How do you design a high-speed digital circuit with enough bypass caps in the right area to supply all the peak power demands? You can’t listen to all the expert advice because it seems they can’t even agree! This presentation covers power distribution network basics and shows three approaches with simulation results for each, and some real-world experience and advice on bypassing for high-speed circuits.
When signals start to get affected by the physical characteristics of the PCB, things start to get a little tricky. A simple point-to-point connection won’t be enough to keep the integrity of the signal. High-speed PCB design focuses on addressing this issue by altering the physical conditions of and around the traces concerned. This study is focused on an FPGA mezzanine card (FMC) carrier supporting the Software-Defined Radio (SDR) System-On-Module (SOM) from Analog Devices. It uses the peripheral component interconnect express (PCIE) topology that consists of both a transmitter pair and a receiver pair. These pairs send and receive signals, in this case, at rates up to 16Gb/s. For these signals to retain their integrity, a thorough high-speed PCB design must be implemented. But there are limitations that prevent easy high-speed routing for this design. Since this FMC is the carrier board for an RF SOM and is designed for compatibility with an industry standard form factor for high pin count (HPC) FMC, there are components that are fixed and cannot be moved or rotated freely. With limited freedom to move components, there are high-speed lines that take longer routes. Longer traces create large current loop areas, increasing the chances for delays and noise. The challenge is to optimize the design’s high-speed lines while taking into consideration the mechanical restrictions, trace lengths, and stackup limitations through simulations. To address these issues, three trials were simulated with the first one sticking to the original design, second with modified differential pair setup and stackup heights, and the third one with modified differential pair return path vias from inline to rectangular and implementation of vias in pads. Insertion loss, return loss, and their eye diagrams were gathered and compared to analyze how each change in the physical characteristics of the board affects the overall signal quality of the lines concerned. Insertion loss improved by -13dB, return loss by -21dB, and the eye diagram widening up to almost twice the size from the original. Note: A small change in the design’s copper features contributed greatly to achieve the performance required from this application. With these results, it can be concluded that it doesn’t take rocket science to handle high-speed signals. With small changes and proper execution, PCB designers will be able to deliver a quality design, all while considering overall cost and board manufacturability.
Understanding millimeter-wave (mmWave) concepts can benefit RF designers, high-speed digital circuit designers and fabricators. In the RF industry, as frequency increases many circuit properties become increasingly difficult to control. Circuits used at mmWave frequencies (above 30GHz) have smaller wavelengths. Due to this small wavelength, circuit performance can be affected by very small circuit anomalies that in the past could have been ignored at lower frequencies. These small circuit anomalies can be caused by a variety of issues, such as normal variations of several processes for PCB fabrication, circuit designs being sensitive to the anomalies and normal variation of certain high-frequency material properties. This presentation will give a basic overview of what to consider in order to optimize the circuit performance at mmWave frequencies. For high-speed digital circuits, the presentation will include information on how mmWave concepts can be used to optimize high-speed digital circuits as the Nyquist frequencies approach the RF mmWave frequencies.
The material presented will be focused on the physics of electromagnetic energy basic principles, presented in easy-to-understand language with plenty of diagrams. Attendees will discover how understanding the behavior of EM fields can help to design PCBs that will be more robust and have better EMC performance. This is not rocket science, but an easy to understand application of PCB geometry. It’s all about the space!
The objective of this tutorial is to guide design teams through the process of evaluating and selecting the right laminate for a design, creating PCB stackups that meet the requirements of complex, multilayer boards that work right the first time, within budget, and with reproducible results across multiple fabricators. The course will go into detail on tradeoffs between loss and cost, including dielectric loss, resistive loss, surface roughness, as well as glass-weave skew. After attending this course, students will be knowledgeable of PCB laminate tradeoffs, the laminate-materials market, and the process of troubleshooting problematic stackup designs. Attendees will also be exposed to cost-effective strategies for controlling loss and glass-weave skew.
As most engineers and designers are aware, EMI occurs because some mechanical structure, within or attached to our system, is capable of resonating and radiating electromagnetic field energy. Those mechanical structures can be a cable attached to the housing around our circuit boards, a part of the metal chassis, a slot in the chassis or a portion of one of the circuit boards in the system. Knowing how to control these structures so they are not capable of supporting resonance and radiation is the key to success.
This two-hour course will discuss basic physics of energy movement, metal vs. plastic enclosures, slots and openings in enclosures, shielding enclosures, shielding of components, proper shielding of cables, basic component placement for MEs, extreme importance of I/O connector placement, routing of external cables, position of cables inside the system, multiple boards in the system — best arrangement, using chassis as a heatsink, other items MEs and PCB designers need to know about PCBs and the system.
Have you ever had a noise-sensitive circuit and tried to find the noise source? Even after you completely encased sensitive portions in all sorts of shielding, you still had noise? It’s very possible this is magnetic noise. Lower frequency magnetic fields can’t be contained and shielded against in the same way electric fields can. In this presentation, hear about the author’s nine-month long battle with a specific magnetic noise issue, the best tools to fight it, twisted pair, current loops, and the best ways to test for and defeat magnetic noise in your designs. New this year is more on how electric fields compare and some general shielding examples.
Raise the shields, Scotty! Starting with some simple definitions for ESD/EOS, this session describes the important differences in the energy involved and the type of damage that can result. The presentation focuses on PCB design techniques as a means of improving system robustness.
A step-by-step guideline for determining the PCB design requirements based on device energy consumption requirements. Wave cycle times and transmission line capacity form the basis of this philosophy. The course will center on the LS1043 Network processor, with a focus on the core power supply requirements (7 A/[U]S). The session will begin with a review of EM field behavior and transmission line design, then will outline a process for analyzing the real power delivery challenge posed by a high-performance microprocessor. Starting with the DC current specification, we will use the device package pinout to determine the necessary PCB networks required to support the delivery of power to the device. The package pinout and clock frequency will be used to determine the real “coulombs per wave cycle” that the PDN must support. This will then be used to design both local storage requirements and connecting structures. A spreadsheet will be presented for performing quantitative analyses of the transmission line capability based on the impedance and length, determining the number of wave cycles needed to deliver the required charge. This perspective can be used in the initial design phase or to evaluate existing designs. EMC test results from a production design, MPC-LS-VNP-MOD, using this approach, will be presented.
Power distribution in PCBs is the foundation around which all things work in the circuit. If this is not designed correctly, the entire circuit is at risk from noise and signal integrity issues, to say nothing of the severely increased possibilities of EMI. Low impedance in the structure, across the harmonic frequency range of a digital circuit is critical. A number of subtle layout techniques will have major impact on power bus impedance, inductance in particular. This 3.5-hour course will cover power bus target impedance, inductance of vias, planes and capacitors, mounting inductance of capacitors, energy delivery to IC cores, the “Bandini Mountain,” best mounting of capacitors based on board stack-up, the importance of IC pinout, placement of decoupling in both low-layer-count and high-layer-count boards, real performance of capacitors (vs. myth), how much decoupling, multiple capacitor values, how to minimize anti-resonant peaks, ferrites in the power bus, analog and RF decoupling, the importance of power/ground plane pairs, ultra-thin power and ground plane pairs and the importance of board stack.