With this presentation, attendees will learn how materials matter in the 5G-world. From rigid laminates, copper styles and properties, flex materials, sintered paste OrMet for any-layer vias: all play a part of the design, manufacturing and performance of products. Attendees will receive a good understanding of basic EM theory, with a strong emphasis on material selection. This will cover aspects affecting interconnections and their respective EM fields. The design flow is from the start of the layout cycle all the way to the generation of deliverables and then into manufacturing. Emphasis is on the role that materials play to make a circuit cost-effective, perform well and be a reliable high-yield product. We will touch on all types of circuit technologies in many market segments. Focus is on integration between design and manufacturing early in the development cycle, to build a high-reliability product that is correct-by-construction and performs on Revision-1.
Signal degradation on PCB transmission lines manifests in many forms: undershoot, overshoot, ringing, pulse shape distortion, switching noise, attenuation, ground bounce, skew, etc. All these can be attributed to one or more of these sources: signal reflections caused by characteristic impedance discontinuities; signal distortion due to conductor and dielectric losses resulting from PCB materials’ properties as signals travel over the transmission lines; crosstalk from signals on nearby PCB conductors; noise in power distribution network; electromagnetic interference (EMI). Impedance discontinuities manifest from many sources, to name a few: unmatched loads and terminations, non-uniformity in the lines, vias, stubs, component and test pads, gaps in reference planes and poorly designed return paths, stray capacitances and inductances, and branching of signal paths, and all these cause signal reflections. Frequency dependence of the copper and dielectric losses cause unequal attenuation of various frequency contents in the signals, causing signal rise time degradation, and variations in dielectric constant with frequency cause different frequency signal components traveling at different speeds.
Crosstalk from nearby conductors occurs due to inductive and capacitive coupling, causing several issues: near- and far-end crosstalk, switching noise, ground bounce, etc. PDN noise and unwanted electromagnetic energy will superimpose on signals causing signal integrity issues. After identifying the root cause, one can find solutions to the signal integrity problem.
What is a wire? At high speeds, it behaves very differently from what we were taught in college. This presentation on high-speed basics makes the subject intuitive in a way that’s easily understood. Learn about how frequency enters the picture, high-speed signal propagation, impedance, noise, and reflections with easy-to-understand animations and analogies to understand this subject on a deeper level.
This presentation will present a simple EM physics and geometry-based approach to designing power distribution networks on PCBs. From input power connection to the IC die, the simple rules discussed can be used to reduce power supply noise and improve EMC. New research is presented on the impact of discrete components on radiated and conducted emissions, with an emphasis on cost analysis. This course will, after an introduction to EM field behavior, describe several effective methods for designing the spaces used to deliver power on a PCB. These methods are driven by considerations for how fast the switches are changing states and the geometry of the spaces and placement of components to properly delivery energy to prevent EMC and signal integrity issues.
When time-varying (AC) signals travel in the transmission lines of a board, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years ICs with very fast rise time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding will help contain and control fields, making noise and EMI issues virtually nonexistent. This 3.5-hour course will focus on the issues PCB designers and engineers need to know to prevent noise, EMI and grounding problems in today’s circuits. We will discuss what is meant by “grounding,” where energy travels in the board, location of high- and low-frequency currents, keys to controlling common mode EMI, cables and other unintended radiators, effects of IC style and packaging on overall grounding, impact of connector pin-out, best locations for IO connectors, divided planes and plane islands in the PCB, routing to control noise, best board stack-ups and filtering of single-ended and differential I/O lines.
How do you design a high-speed digital circuit with enough bypass caps in the right area to supply all the peak power demands? You can’t listen to all the expert advice because it seems they can’t even agree! This presentation covers power distribution network basics and shows three approaches with simulation results for each, and some real-world experience and advice on bypassing for high-speed circuits.
When signals start to get affected by the physical characteristics of the PCB, things start to get a little tricky. A simple point-to-point connection won’t be enough to keep the integrity of the signal. High-speed PCB design focuses on addressing this issue by altering the physical conditions of and around the traces concerned. This study is focused on an FPGA mezzanine card (FMC) carrier supporting the Software-Defined Radio (SDR) System-On-Module (SOM) from Analog Devices. It uses the peripheral component interconnect express (PCIE) topology that consists of both a transmitter pair and a receiver pair. These pairs send and receive signals, in this case, at rates up to 16Gb/s. For these signals to retain their integrity, a thorough high-speed PCB design must be implemented. But there are limitations that prevent easy high-speed routing for this design. Since this FMC is the carrier board for an RF SOM and is designed for compatibility with an industry standard form factor for high pin count (HPC) FMC, there are components that are fixed and cannot be moved or rotated freely. With limited freedom to move components, there are high-speed lines that take longer routes. Longer traces create large current loop areas, increasing the chances for delays and noise. The challenge is to optimize the design’s high-speed lines while taking into consideration the mechanical restrictions, trace lengths, and stackup limitations through simulations. To address these issues, three trials were simulated with the first one sticking to the original design, second with modified differential pair setup and stackup heights, and the third one with modified differential pair return path vias from inline to rectangular and implementation of vias in pads. Insertion loss, return loss, and their eye diagrams were gathered and compared to analyze how each change in the physical characteristics of the board affects the overall signal quality of the lines concerned. Insertion loss improved by -13dB, return loss by -21dB, and the eye diagram widening up to almost twice the size from the original. Note: A small change in the design’s copper features contributed greatly to achieve the performance required from this application. With these results, it can be concluded that it doesn’t take rocket science to handle high-speed signals. With small changes and proper execution, PCB designers will be able to deliver a quality design, all while considering overall cost and board manufacturability.
Understanding millimeter-wave (mmWave) concepts can benefit RF designers, high-speed digital circuit designers and fabricators. In the RF industry, as frequency increases many circuit properties become increasingly difficult to control. Circuits used at mmWave frequencies (above 30GHz) have smaller wavelengths. Due to this small wavelength, circuit performance can be affected by very small circuit anomalies that in the past could have been ignored at lower frequencies. These small circuit anomalies can be caused by a variety of issues, such as normal variations of several processes for PCB fabrication, circuit designs being sensitive to the anomalies and normal variation of certain high-frequency material properties. This presentation will give a basic overview of what to consider in order to optimize the circuit performance at mmWave frequencies. For high-speed digital circuits, the presentation will include information on how mmWave concepts can be used to optimize high-speed digital circuits as the Nyquist frequencies approach the RF mmWave frequencies.
The material presented will be focused on the physics of electromagnetic energy basic principles, presented in easy-to-understand language with plenty of diagrams. Attendees will discover how understanding the behavior of EM fields can help to design PCBs that will be more robust and have better EMC performance. This is not rocket science, but an easy to understand application of PCB geometry. It’s all about the space!
The objective of this tutorial is to guide design teams through the process of evaluating and selecting the right laminate for a design, creating PCB stackups that meet the requirements of complex, multilayer boards that work right the first time, within budget, and with reproducible results across multiple fabricators. The course will go into detail on tradeoffs between loss and cost, including dielectric loss, resistive loss, surface roughness, as well as glass-weave skew. After attending this course, students will be knowledgeable of PCB laminate tradeoffs, the laminate-materials market, and the process of troubleshooting problematic stackup designs. Attendees will also be exposed to cost-effective strategies for controlling loss and glass-weave skew.