Flexible, Affordable Electronics Education
Online courses and webinars for the printed circuit engineering community.

The Butterfly Effect in PCB Design: Optimization of High-speed Lines for an FMC Carrier Board


Jamie Pacamarra
Analog Devices

 0 min 0 sec video

When signals start to get affected by the physical characteristics of the PCB, things start to get a little tricky. A simple point-to-point connection won’t be enough to keep the integrity of the signal. High-speed PCB design focuses on addressing this issue by altering the physical conditions of and around the traces concerned. This study is focused on an FPGA mezzanine card (FMC) carrier supporting the Software-Defined Radio (SDR) System-On-Module (SOM) from Analog Devices. It uses the peripheral component interconnect express (PCIE) topology that consists of both a transmitter pair and a receiver pair. These pairs send and receive signals, in this case, at rates up to 16Gb/s. For these signals to retain their integrity, a thorough high-speed PCB design must be implemented. But there are limitations that prevent easy high-speed routing for this design. Since this FMC is the carrier board for an RF SOM and is designed for compatibility with an industry standard form factor for high pin count (HPC) FMC, there are components that are fixed and cannot be moved or rotated freely. With limited freedom to move components, there are high-speed lines that take longer routes. Longer traces create large current loop areas, increasing the chances for delays and noise. The challenge is to optimize the design’s high-speed lines while taking into consideration the mechanical restrictions, trace lengths, and stackup limitations through simulations. To address these issues, three trials were simulated with the first one sticking to the original design, second with modified differential pair setup and stackup heights, and the third one with modified differential pair return path vias from inline to rectangular and implementation of vias in pads. Insertion loss, return loss, and their eye diagrams were gathered and compared to analyze how each change in the physical characteristics of the board affects the overall signal quality of the lines concerned. Insertion loss improved by -13dB, return loss by -21dB, and the eye diagram widening up to almost twice the size from the original. Note: A small change in the design’s copper features contributed greatly to achieve the performance required from this application. With these results, it can be concluded that it doesn’t take rocket science to handle high-speed signals. With small changes and proper execution, PCB designers will be able to deliver a quality design, all while considering overall cost and board manufacturability.

Recommended Audience:
Speaker  :  
Rick Hartley
Company : 
RHartley Enterprises
Power distribution in PCBs is the foundation around which all things work in the circuit. If this is not designed correctly, the entire circuit is at risk from noise and signal integrity issues, to...
Speaker  :  
Daniel Beeker
Company : 
NXP Semiconductor
Tired of failing EMC certification over and over? Join the crowd. Shrinking IC geometries and a resulting increase in switching speeds make designing compliant printed circuit boards more...
With the advent of ICs with multiple power rails at very high currents, the design of the power delivery system in a modern product is often more difficult than routing the PCB to ensure good signal...

Printed Circuit University offers Flexible, Affordable Electronics Education. We offer online classes from some the top professionals in their fields

Don't have an account yet? Register Now!

Sign in to your account