Circuit boards for the IoT world (Internet of Things) are often driven by the need for low power dissipation, low cost (which drives very low layer count), moderate to high-density and mixed-signal applications. This combination of needs can make board design an extreme challenge. Creating a 1-, 2- or 4-layer board, with excellent signal integrity and low noise/interference and no EMI issues can, by itself, be a very serious challenge. This 3.5-hour course will discuss how to understand when it is necessary to control impedance of lines, how to do it cost-effectively, proper setup of routed lines to keep circuit energy from spreading (preventing interference), even on a one layer board, design of antenna into the PCB, circuit grounding in low layer count boards, power distribution without the benefit of power planes, ground bounce, cross talk with low layer count and design to optimize manufacturability of low layer count PCBs.
This half-day course is an overview (past, present, and future) of the interactions of processes, people and technologies involved in the complete lifecycle of a PCB design. This course is designed to provide a solid foundation for those who are just starting out (zero to two years of experience) as a PCB designer and help the individual formulate a roadmap to build their knowledge base for both personal and career advancement as contributors to this industry. All attendees will receive an MS Excel checklist of the traditional questions that PCB designers should ask throughout the PCB design process.
Supply voltages decrease with every new silicon generation, contributing as well to the goal of reducing power consumption of our electronics. Coupled with the resulting shrinking noise margins for these ICs, this defines increasing demands for the quality and stability of power distribution schemes of PCBs. Hence, tighter requirements and constraints from silicon vendors are defined for power distribution networks (PDN), which PCB designers follow, in conjunction with tighter decoupling schemes. Board real estate limitations, application-dependent restrictions (e.g., discrete package size allowance in automotive) and cost demands further complicate the game. To address these technical challenges, engineers need to evolve from working within a disconnected design process to new or advanced design methodology with power-integrity and the demands of the PDN in mind. Using such a methodology and smart mechanisms to optimize the decoupling scheme can help ensure a design will meet the electrical specifications for power. In this two-hour workshop, the requirements and basics of PCB power distribution systems are explained in detail. The whole problem area, ranging from DC (with aspects like IR-drop, DC voltages and current distributions) to AC with its phenomena (e.g., target impedance, decoupling, inductance), is covered. Topics like plate capacitance, loop inductance and cavity resonance are explained in detail but without deep math. Side effects to the signal integrity and EMC behavior of board structures are discussed using illustrated practical examples. The role of capacitors, their parasitic behavior (ESL, ESR, connection inductance) and the technical decoupling evolution in recent years are a major part of the workshop. Guidelines for a first order covering and resolving power integrity issues are provided, regardless of the PCB design and ECAD process. Simulation capabilities addressing power integrity during PCB design will be explained and demonstrated by slides in a generic vendor-neutral manner as a problem-solving approach. Silicon vendor support documents (e.g. constraint and spreadsheet tools) to address power integrity are introduced and briefly discussed. Examples from various industries (e.g., automotive, industry automation, IoT) will complement the session with practical application experience.
Topics covered: 1. BGA/CSP process technologies and standards; single die BGA and FBGA packaging, flip-chip and die-size package technologies, wafer level packaging (WLP), fan-out wafer-level packaging (FOWLP), JEDEC package outline standards. 2. Innovative solutions for 2D, 2.5D and 3D packaging, 2D BGA package technology, 3D multiple die and stacked package methodologies, implementing 2.5D for high-density BGA applications, silicon-based interposer structure, glass-based interposer structures, organic (laminate) based interposer structures. 3. Printed circuit board design guidelines for HDI, ball grid array (BGA), fine-pitch ball grid array (FBGA and DSBGA), flip-chip (WLP/FOWLP), 2.5D interposer structures; 4. HDI circuit and microvia design implementation, HDI circuit fabrication variations, microvia process methodology, design guidelines for HDI circuits, HDI sources and economic issues. 5. Specifying PCB base material, surface finish and coatings, organic-based material selection criteria, specifying thickness of copper foils, surface plating and coating variations, solder mask process considerations; 6. Preparation for high-volume assembly processing, surface mount assembly process overview, basic features needed for SMT assembly processing, system requirements for BGA and CSP device placement, palletizing to maximize assembly process efficiency, assembly process implementation.
When designing a PCB, the signal routing and its return are critical to the circuit working properly. Great care is usually given to routing the signals, but often the return portion is the last thing considered, or sometimes it is forgotten altogether. This presentation will talk about the importance of designing that return path, with a discussion of the physics involved, where the energy flows, the interference caused when it is not controlled, and the planes and stackup needed. Additionally, we will discuss the best ways to contain energy fields, the spacing that helps prevent problems, and the routing and return movement from layer to layer. Throughout, we will discuss some signal routes and look at the paths that might set up the best possibility for a clean return.
A differential pair is any two transmission lines. When each transmission line has a return plane, its pretty clear how the differential impedance is related to the geometry. But what if there is no return plane? How do we think about the differential impedance of a differential pair when we remove the return plane, like in a twisted pair? What quality influences the differential impedance and how do we go about measuring the differential impedance? What is really different between two transmission lines with a return plane and a twisted pair with no return plane? We will explore these questions using essential principles, 2D field solvers and TDR measurements.
When creating libraries, standards are crucial for maintaining consistency, accuracy, and reliability. Yet, even with rigid standards in place, mistakes inevitably creep into such a detail-oriented process. In this talk, we’ll explore some hair-raising footprint horror stories and how to avoid fatal footprint mistakes on your next PCB design. Delving far beyond the basics, we’ll look at the more gnarly errors that trip up engineers. For example, we all know to double-check our pin mappings, but what about how you have interpreted the component’s orientation in the datasheet? Misinterpreting a component’s top view for its bottom view is one of the top causes of bad boards that we see. Drawn from our community of 200,000 engineers, our hope is these lessons will prevent costly prototype iterations and delays on your next project. Finally, we’ll explore how to prevent these errors on your next designs. For example, by bringing in more verification into your processes through checklists or by creating an automated system for assessing the quality of your PCB footprints.
There are many ways to route a PCB, some much more effective for signals than others. The first design rule is that the board must work properly, so it is important to have a plan that addresses good signal quality and crosstalk control, no matter what the frequency. In this presentation, we will start with a bit of the science to set up the reasoning for routing a certain way, then move into return current and impedance control, with a discussion of what affects those things. Starting route with an effective fanout plan sets up what is to come, and we will also explore general routing priorities and concerns. To avoid problems, routing schemes will be addressed, along with spacing, differential pair and length matched routing. Last, pros and cons of hand routing, semiautomation, and autorouting will be examined.
Some experts say you should never use a split ground plane. Others say you should use a split ground plane to control noise. When is the right time to split a ground plane? We will explore the impact of a split plane on reducing cross talk and demonstrate with a simple measurement the problem a split ground plane solves really well. Then we’ll look at why, if your design needs to take advantage of the reduced cross talk with a split plane, you are designing your product wrong.
This is a session for embedded engineers and PCB designers who have never done RF board layout but are curious and want to have a go at it. It is not for experienced microwave engineers. This practical workshop will introduce (or reintroduce) basic math associated with the topic, but the goal is to be practical and intuitive, not theoretical and esoteric. We will visualize the elements available and build and test using desktop prototyping gear.
The class is broken into two sessions (morning and afternoon). Session 1: Back to basics electromagnetic recap; transmission lines – what you need to know; EM and T-line visualizations; PCB materials and conductors for RF and microwave. Session 2: Essential transmission line evaluation skills (VSWR, S-parameters, basic simulation and visualization); introduction to the Smith chart, and how to match impedance; practical design exercise with introduction to the VNA; using the desktop CNC to mill practical prototypes (and tips to mill with accuracy); introduction to PCB antenna types.