A step-by-step guideline for determining the PCB design requirements based on device energy consumption requirements. Wave cycle times and transmission line capacity form the basis of this philosophy. The course will center on the LS1043 Network processor, with a focus on the core power supply requirements (7 A/[U]S). The session will begin with a review of EM field behavior and transmission line design, then will outline a process for analyzing the real power delivery challenge posed by a high-performance microprocessor. Starting with the DC current specification, we will use the device package pinout to determine the necessary PCB networks required to support the delivery of power to the device. The package pinout and clock frequency will be used to determine the real “coulombs per wave cycle” that the PDN must support. This will then be used to design both local storage requirements and connecting structures. A spreadsheet will be presented for performing quantitative analyses of the transmission line capability based on the impedance and length, determining the number of wave cycles needed to deliver the required charge. This perspective can be used in the initial design phase or to evaluate existing designs. EMC test results from a production design, MPC-LS-VNP-MOD, using this approach, will be presented.