This course is intended to provide the participant an understanding of how design issues interact with the SMT assembly processes. How design affects manufacturing capability and vice versa is covered in depth. It looks at the design impact on SMT assembly, component placement, soldering, paste and final finish considerations, and manufacturing implications of emerging technologies including BTCs, ultra-miniature passives, and ultra-fine pitch IC packages.
The new IPC Digital Twin standard (IPC-2551) defines an interoperable framework in which thousands of applications from multiple sources work seamlessly together, providing the opportunity for virtual prototyping of all aspects of design, manufacturing and beyond. Use of IPC-2551 prevents companies in all areas of the industry from making the mistake of tying themselves to any monopolistic data exchange technology. The impact of the IPC Digital Twin on the design through manufacturing flow will be significant, and will be the area that develops sooner than any other, built upon and driven by existing IPC standards, such as IPC-2581 (DPMX), IPC-2591 (CfX) and IPC-1782 internal and external (secure supply-chain) traceability. This presentation explains the IPC Digital Twin standard, using some specific use-case examples that illustrate the value and opportunity that the standard provides to both the design and manufacturing communities, exchanging digital models bidirectionally between design and manufacturing. This presentation will be of critical interest to all of those involved in design and manufacturing, including business management, engineers and technology providers.
This comprehensive seminar of how to design a PCB stackup to optimize performance while attaining the lowest cost possible. With the advent of very high-speed signaling along with multiple very high-current power supply rails, it is necessary to understand how materials behave and how PCBs are fabricated in order to arrive at a PCB stackup that results in a “right the first time” design. The seminar draws from the speaker’s long experience designing PCB stackup for products ranging from video games to supercomputers. It draws on the results of dozens of test PCBs used to characterize materials from a loss and high-speed skew perspective.
With an estimated 80,000 SMTP lines in use standards are a lifeline for line operators and equipment and software developers worldwide. SEMI is developing a suite of standards for SMT and PCBA assembly lines. The new SMT Equipment Link Standards (SEMI SMT-ELS) or SEMI A1, A1.1 and A2 address Horizontal Communication (HC) between different equipment on the line and Vertical Communication (VC) between equipment and higher-tier hosts, including, for example, a line controller/equipment host or a factory automation host. SEMI is well-known for its SECS/GEM/EDA standards, which are almost universally adopted in the front-end processing fabs where frequent job changes and recipe changes are common. The SMT-ELS suite adjusts to the specific needs of SMT lines, including more operator interaction, minimal data collection requirements, material metadata handoffs between equipment, and minimal queuing. This presentation goes into detail on the design and features of SMT-ELS, including set up time and configurations.
Differential pairs have been used in PC boards for years to carry high-speed serial and high-speed parallel data, in a variety of bus formats. Many board designers and engineers believe the rules for differential pairs are the same in a PCB as they are in cable or twisted pairs of wires. This is usually not the case!
This course will cover the advantages of differential pairs vs. single-ended lines, which differential pair format gives the best impedance control, what is the right spacing between the lines of a pair, crosstalk between differential pairs, what is important in differential pair routing, how much timing skew is really acceptable, the impact of material type and the impact of vias on signal integrity and EMI.
This session is intended for board designers to understand the things RF engineers request during PCB layout. Experienced RF engineers will likely not learn anything new from this course, as the material is mainly geared to board designers.
Due to sensitivity in analog circuits, the keys to full functionality (whether you are designing very high-frequency analog PC boards, mixing RF with digital or mixing low-frequency analog with digital) are signal integrity and noise control in the design of the printed circuit board. This course will cover differences between analog and digital, circuit changes over time, lumped vs. distributed length lines, reflections/return loss/VSWR, low- and high-frequency current, transmission line behavior, impedance control, microstrip vs. stripline, coplanar waveguide w/ ground, circuit termination, 1/4 wavelength couplers and filters designed into board copper, layout techniques and strategies, critical routing and circuit isolation, ground plane splitting (when to and when not to), mismatched loads and other discontinuities, signal splitters, tuning transmission lines, power bus decoupling for RF vs. digital circuits and board stack-ups for mixed RF and digital circuits.
This course will address advanced problem solving of printed wiring board defects. Some defects, such as interconnect separation, delamination, wedge voids, plating folds, micro-voids, surface pitting, and hole wall pull-away, carry significant costs. Many are difficult to solve because the root cause may not be readily apparent, and multiple factors may contribute. This course will explore the most intricate of these factors and how the interrelationship of up- and downstream processes contribute to scrap product. What effect does drilling have on hole wall quality and the subsequent metallization process? Participants will learn how to recognize problems like this and take corrective action. The course will explore a myriad of electrodeposition defects, such as mouse bites, pitting, and domed or crown plating. Solderability and assembly-related issues such as outgassing, black pad, creep corrosion and blow holes will also be discussed. The course will conclude with a discussion on imaging, including liquid-photoimageable solder masks. Strategies to solve solder mask peeling, poor circuit trace coverage, skips, bubbles, and poor adhesion in nickel gold plating will be discussed. Solder mask equipment and its effect on solder mask quality will also be explored. In addition, over 200 images of defects will be presented.
Attendees will learn how to recognize and solve lamination and other multilayer-related defects; electrodeposition defects: mouse bites, pitting, nodules, crown or dome plating, dog bone defects; copper plating reliability; how to improve plating distribution and throwing power; metallization: microvoids/voiding, interconnect separation, hole wall pull away, and assembly issues; black pad phenomenon: new details on its cause and how to eliminate it; imaging: defects, surface preparation, solder mask issues and defects, process control. Also covered will be other final finish-related defects: creep corrosion, champagne bubble effect, solder mask interfacial attack. Participants should have some knowledge of the PCB fabrication process. This course will directly benefit those involved in printed circuit board fabrication and assembly. In addition, PCB end-users and designers will gain significant knowledge about PCB-related defects.
Tired of failing EMC certification over and over? Join the crowd. Shrinking IC geometries and a resulting increase in switching speeds make designing compliant printed circuit boards more challenging than ever. We need a new design methodology to change this unacceptable status quo, one based on electromagnetic field physics. This training module presents a basic introduction to EM fields and provides guidelines for building successful, cost-effective printed circuit boards. This presentation includes example designs and test results.
With the advent of ICs with multiple power rails at very high currents, the design of the power delivery system in a modern product is often more difficult than routing the PCB to ensure good signal integrity. The power delivery system must deliver power to devices at frequencies from D to hundreds of megahertz. The application notes that accompany most ICs do not contain adequate information to allow a designer to get the PDS correctly designed.
This course is aimed at providing the information needed to get the job done right. It draws on the speaker’s experience designing hundreds of power delivery systems for products ranging from satellites to super computers. It contains a very large number of test PCBs used to determine how well each component will perform when used in a PDS.
This presentation will offer a complete view of place-and-route for dense high-speed and RF circuits. We will cover a wide range of topics, including next-generation materials, the rational for considering HDI for our products, and overall layout flow. We will discuss the technological challenges we face in both the schematic circuit rules capture, design layout and manufacturing process. Students will learn what it takes to satisfy solvability, high-speed concerns, and RF performance issues, while building a board that will be cost-effective as a reliable high-yield product. We will also review how our early integration with the manufacturing team during the design cycle will help us understand the specifics to build a product that is correct-by-construction and performs on revision-1. The focus will be on practical application and implementation using real-world examples.